The present technique relates to the efficient utilisation of an address translation cache.
It is known to provide data processing systems which incorporate an address translation cache, such as a translation lookaside buffer (TLB), to store address translation data relating to the translation of, for example, virtual addresses to physical addresses. The address translation data can also provide attribute data regarding the memory accesses being made, such as permission data and memory attributes. Whilst the provision of an address translation cache is useful in improving performance by reducing the number of slow page table walks required, such an address translation cache can occupy significant circuit resources, and accordingly it is desirable to make efficient utilisation of those resources. It is also useful to ensure that a lookup operation performed within the address translation cache can be performed quickly so as to optimise the performance benefits achievable from the use of such an address translation cache.
Each item of address translation data stored within an address translation cache can have an associated page size indication, and one way to seek to increase the effective capacity of an address translation cache is to allow the address translation cache to hold address translation data for more than one page size. However, this can complicate the lookup process used to determine whether the address translation cache holds address translation data for a specified virtual address, and hence can impact performance.
It would be desirable to provide a mechanism that could allow efficient utilisation of an address translation cache without adversely affecting performance.